Logic circuit with improved switching

ABSTRACT

A fundamental logic circuit used, for example, in an electronic computer, comprising an output inverter transistor and a switching transistor which discharges a base charge stored in a storage capacitance in a base-emitter junction of the output inverter transistor when the output inverter transistor changes from the turned on condition to the turned off condition.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The present invention relates to a fundamental logic circuit and, moreparticularly, to a high speed fundamental logic circuit used, forexample, in an electronic computer.

(2) Description of the Prior Art

In a fundamental logic circuit such as an inverter or a NAND gate havingan output inverter transistor whose emitter electrode is grounded, oneof the most important factors influencing the operating speed of thefundamental logic circuit is the turn off time of the output invertertransistor. In order to reduce the turn off time of the output invertertransistor, it is necessary to quickly discharge the charge stored inthe base region of the output inverter transistor.

FIG. 1 illustrates a TTL inverter circuit as an example of aconventional fundamental logic circuit which has an output invertertransistor. In FIG. 1, an input transistor Q₁ is an NPN type transistorwhich switches current flowing from the positive voltage source V_(cc)through a resistor R₁ to the base electrode of the input transistor Q₁to an input terminal IN or to the base electrode of a driver transistorQ₂. The driver transistor Q₂ is an NPN type transistor which outputsboth inverted and non-inverted signals of an input signal applied to theinput terminal IN. An output inverter transistor Q₃ is an NPN typetransistor which is driven by an output signal from the emitterelectrode of the driver transistor Q₂. Transistors Q₄ and Q₅ are bothNPN type transistors which constitute a Darlington transistor driven byan output signal from the collector electrode of the driver transistorQ₂. The transistor Q₅ serves as a level shift circuit which provides apotential difference between the emitter electrode of the transistor Q₄and the collector electrode of the output inverter transistor Q₃, i.e.,the output terminal OUT, and the level shift circuit can be replaced bya diode connected therebetween. The output inverter transistor Q₃ andthe Darlington transistor consisting of the transistors Q₄ and Q₅constitute an output stage having a so-called totem-pole structure.

The TTL inverter circuit of FIG. 1 is well known and, therefore, thegeneral description of the operation thereof is omitted herein, and theoperation thereof will be described for a condition wherein the outputpotential of the output terminal OUT changes from low (i.e. about 0.4 V)to high (i.e. about 3.4 V, which is the potential of the voltage sourceV_(cc) -2 V_(BE)). When the potential of the input terminal IN changesfrom high to low, the driver transistor Q₂ changes from the turned oncondition to the turned off condition. Therefore, the potential of apoint A, i.e., the collector electrode of the transistor Q₂ changes fromlow to high, and the potential of the emitter electrode of thetransistor Q₂ changes from high to low. Accordingly, the transistor Q₃begins to change from the turned on condition to the turned offcondition. However, turning off of the transistor Q₃ is not completeuntil the base charge stored in the base region of the transistor Q₃ isdischarged and the transistor Q₃ remains in the turned on conditionuntil the base charge is completely discharged. In order to dischargethe base charge stored in the base region of the transistor Q₃, aresistor R₅ is connected between the base electrode and the emitterelectrode (i.e. the ground) of the transistor Q₃, so that a dischargepath is constituted. Therefore, although the discharge time of the basecharge can be reduced by decreasing the resistance value of the resistorR₅, it is impossible to greatly decrease the resistance value of theresistor R₅. This is because, when the transistor Q₃ is turned on, theresistor R₅ provides a bypass for the base current of the transistor Q₃to the ground, and if the resistance value of the resistor R₅ is verysmall, the base current becomes too small to turn on the transistor Q₃completely. Therefore, in the logic circuit of FIG. 1, the turn off timeof the output inverter transistor Q₃ cannot be very small.

Moreover, the conventional logic circuit of FIG. 1 has the disadvantageof having a poor transfer characteristic as shown in FIG. 2. Assume thatthe input potential V_(IN) of the input terminal IN increases from lowto high gradually. When the input potential V_(IN) increases in therange from V_(BE2) to V_(BE2) +V_(BE3), the potential of the baseelectrode of the driver transistor Q₂ also increases from V_(BE2) toV_(BE2) +V_(BE3). Wherein, V_(BE2) designates the base-emitter voltageof the transistor Q₂ and V_(BE3) designates the base-emitter voltage ofthe transistor Q₃. In this condition, the driver transistor Q₂ begins tochange from the turned off condition to the turned on condition, so thatthe current passing through a resistor R₂, the main current path of thedriver transistor Q₂ and the resistor R₅ increases gradually. In thiscondition, the potential of the point A, i.e., the collector electrodeof the driver transistor Q₂, falls gradually and, therefore, thepotential of the output terminal OUT falls gradually. This is becausethe transistors Q₄ and Q₅ are in the turned on condition and the outputinverter transistor Q₃ is still in the turned off condition, and thepotential of the point A is transferred to the output terminal OUTthrough the base emitter junctions of the transistors Q₄ and Q₅.Therefore, in the input potential range from V_(BE2) to V_(BE2)+V_(BE3), the transfer characteristic of the conventional logic circuitis not sharp as illustrated in FIG. 2. After the input potential V_(IN)becomes larger than V_(BE2) +V_(BE3), the inverter transistor Q₃ turnson and the output potential V_(OUT) falls to a low level (i.e. about 0.4V) quickly.

FIG. 3 illustrates a two input DTL NAND gate circuit as another exampleof a conventional fundamental logic circuit. The circuit of FIG. 3comprises a diode gate consisting of Schottky barrier diodes(hereinafter referred to as SBD), D₃₁ and D₃₂, and a resistor R₃₁.Transistors Q₃₄ and Q₃₅, which constitute a Darlington transistor, aredriven by an output signal from the collector electrode of a drivertransistor Q₃₂, and an output inverter transistor Q₃₃ is driven by anoutput signal from the emitter electrode of the driver transistor Q₃₂.The Darlington transistor consisting of the transistors Q₃₄ and Q₃₅, andthe output inverter transistor Q₃₃ constitute a totem-pole output stage.The NAND gate circuit of FIG. 3 also comprises a switching transistorQ₃₆ in order to quickly discharge the base charge stored in the baseregion of the output inverter transistor Q₃₃, so that the turn off timeof the transistor Q₃₃ is reduced. The base electrode of the switchingtransistor Q₃₆ is connected to the collector electrode of the drivertransistor Q₃₂ through diodes D₃₃ and D₃₄, and to the ground through aresistor R₃₅.

Operation of the switching transistor Q₃₆ will now be described. Whenthe input potential V_(IN1) and V_(IN2) of both input terminals IN₁ andIN₂ are high, the driver transistor Q₃₂ is turned on and the outputinverter transistor Q₃₃ is turned on. Therefore, the potential of thecollector electrode of the driver transistor Q₃₂ is low, so that thetransistors Q₃₄ and Q₃₅ are both turned off and the potential of theoutput terminal is low. In this condition, the diodes D₃₃ and D₃₄ areturned off, and therefore, the switching transistor Q₃₆ is turned off.

Assume that the input potential of at least one of the input terminalsIN₁ and IN₂ changes to low, then the driver transistor Q₃₂ turns off sothat the potential of the collector electrode of the transistor Q₃₂becomes high. Therefore, the transistors Q₃₄ and Q₃₅ are turned on, andthe output inverter transistor Q₃₃ is turned off. In this condition,current flows from the collector electrode of the driver transistor Q₃₂through the diodes D₃₃ and D₃₄ to the base electrode of the switchingtransistor Q₃₆, and to the ground through a resistor R₃₅. Therefore, theswitching transistor Q₃₆ turns on and quickly discharges the base chargestored in the base region of the output inverter transistor Q₃₃, so thatthe turn off time of the output inverter transistor Q₃₃ is reduced.

However, the conventional logic circuit of FIG. 3 has the followingdisadvantages.

(1) The threshold voltage V_(TH) of each of the input potentials V_(IN1)and V_(IN2) is as follows.

    V.sub.TH =V.sub.CE36 +V.sub.BE32 -V.sub.F ≈0.8 V   (1)

Where V_(CE36) is a saturated collector-emitter voltage (i.e. about 0.4V) of the switching transistor Q₃₆, V_(BE32) is a base-emitter voltage(i.e. about 0.8 V) of the driver transistor Q₃₂ and V_(F) is a forwardbiased voltage (i.e. about 0.4 V) of the diode D₃₁ or D₃₂. Therefore,the threshold voltage V_(TH) becomes about 0.8 V, and is smaller thanthat of a usual TTL gate circuit, so that the logic circuit of FIG. 3has a poor noise immunity.

(2) The current flows from the positive voltage source V_(cc) throughthe resistor R₃₂, the diodes D₃₃ and D₃₄, and the resistor R₃₅ and thebase-emitter junction of the switching transistor Q₃₆ to the ground allthe time the driver transistor Q₃₂ is in the turned off condition.Therefore, the power consumption of the logic circuit is large.

(3) The logic circuit of FIG. 3 uses a large number of semiconductorelements and, therefore, the circuit occupies a relatively large area inan integrated circuit.

Examples of a prior art fundamental logic circuit having an outputinverter transistor are disclosed in the publication "The TTL Data Bookfor Design Engineers" First Edition, by Texas Instruments Incorporated,1973, P. 87 or P. 89.

SUMMARY OF THE INVENTION

It is an object of the present invention to decrease the turn off timeof the output inverter transistor from that of the conventionalfundamental logic circuit so that the operating speed of the fundamentallogic circuit is increased over that of the conventional logic circuit.

It is another object of the present invention to improve the transfercharacteristic of a fundamental logic circuit.

It is still another object of the present invention to decrease thepower consumption of the high speed fundamental logic circuit.

It is further object of the present invention to reduce the areaoccupied by a fundamental logic circuit from the area occupied by theconventional fundamental logic circuit in an integrated circuit.

According to the present invention, there is provided a fundamentallogic circuit comprising a switching transistor which discharges thebase charge stored in the base region of an output inverter transistorwhen the output inverter transistor changes from the turned on conditionto the turned off condition.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating a TTL inverter circuit as anexample of a conventional fundamental logic circuit.

FIG. 2 illustrates a transfer characteristic of the TTL inverter circuitof FIG. 1.

FIG. 3 is a circuit diagram illustrating a two input DTL NAND gate asanother example of a conventional fundamental logic circuit.

FIG. 4 is a circuit diagram illustrating a TTL inverter circuit as afirst embodiment of the present invention.

FIG. 5 illustrates a transfer characteristic of the TTL inverter circuitof FIG. 4.

FIG. 6 is a circuit diagram illustrating a TTL inverter circuit as asecond embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating a fundamental logic circuit asa third embodiment of the present invention.

FIG. 8 is a circuit diagram illustrating a two input DTL NAND gate as afourth embodiment of the present invention.

FIG. 9 is a circuit diagram illustrating another two input DTL NAND gateas a fifth embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

With reference to FIGS. 4 through 9, the present invention will now bedescribed. FIG. 4 illustrates a TTL inverter circuit as a firstembodiment of the present invention. In FIG. 4, the same parts as appearin FIG. 1 are designated by the same reference symbols, and theexplanation thereof is omitted herein. The logic circuit of FIG. 4 doesnot use the resistor R₅ of FIG. 1 and comprises a first switchingtransistor Q₆ of NPN type, whose main current path is connected betweenthe base electrode and the emitter electrode of the output invertertransistor Q₃, and which discharges the base charge stored in the baseregion of the transistor Q₃. The logic circuit of FIG. 4 also comprisesa second switching transistor Q₇ of PNP type, whose main current path isconnected between the base electrode of the first switching transistorQ₆ and the collector electrode of the driver transistor Q₂, and whosebase electrode is connected to the emitter electrode of the transistorQ₄ connected to the base electrode of the transistor Q₅. The collectorelectrode of the second switching transistor Q₇, which is connected tothe base electrode of the first switching transistor Q₆, is connected tothe ground through a resistor R₆.

As aforementioned, when the input potential V_(IN) of the input terminalIN changes from high to low, the driver transistor Q₂ is turned off andthe potential of the collector electrode of the driver transistor Q₂(i.e. point A) changes from low to high. Accordingly, the outputinverter transistor Q₃ starts to change from the turned on condition tothe turned off condition, so that the output potential V_(OUT) starts tochange from low (i.e. about 0.4 V) to high. Before the output potentialV_(OUT) becomes high, a potential difference exists between the point Aand the output terminal OUT, and therefore, a transient current flowsfrom the point A through the base-emitter junction of the transistor Q₄and through the base-emitter junction of the transistor Q₅ to the maincurrent path of the output inverter transistor Q₃, so that thetransistors Q₄ and Q₅ are turned on.

A part of the transient current flows, according to the presentinvention, through the second switching transistor Q₇ and the firstswitching transistor Q₆. That is, the second switching transistor Q₇ issupplied with the base current by the above-mentioned potentialdifference and is turned on. Therefore, a current passes from the pointA through the main current path of the second switching transistor Q₇ tothe base electrode of the first switching transistor Q₆, so that thefirst switching transistor Q₆ is turned on. When the first switchingtransistor Q₆ is so turned on, the base charge stored in the base regionof the transistor Q₃ is discharged through the main current path of thefirst switching transistor Q₆. Therefore, the turn off time of theoutput inverter transistor Q₃ is reduced and the output invertertransistor Q₃ is turned off quickly, thereby changing the outputpotential V_(OUT) to high. In response to the change of the outputpotential V_(OUT) from low to high, the second switching transistor Q₇turns off and, thus, the first switching transistor Q₆ is turned off.Therefore, the transistors Q₆ and Q₇ is turned on only for a short timeand steady current consumption of the logic circuit of FIG. 4 isreduced.

FIG. 5 illustrates the transfer characteristic of the logic circuit ofFIG. 4. As illustrated in FIG. 5, the logic circuit of FIG. 4 has asharper transfer characteristic than that of the conventional logiccircuit of FIG. 1 illustrated in FIG. 2. When the input potential V_(IN)changes from low to high, the driver transistor Q₂ is turned on.However, since the logic circuit of FIG. 4 does not have the resistorR₅, contained in the conventional logic circuit of FIG. 1, the drivertransistor Q₂ turns on at substantially the same time as the turn on ofthe output inverter transistor Q₃ after the input potential has reachedto the level of V_(BE2) +V_(BE3). Therefore, the potential of the pointA remains substantially at high level until the input potential V_(IN)reaches the level of V_(BE2) +V_(BE3), and after the input potential hasreached to the level of V_(BE2) +V_(BE3), the potential of the point Afalls to low quickly, and thus, the output potential V_(OUT) falls tolow quickly. Consequently, the transfer characteristic of the logiccircuit of FIG. 4 becomes very sharp.

FIG. 6 illustrates a TTL inverter circuit as a second embodiment of thepresent invention. The TTL inverter circuit of FIG. 6 also comprises thefirst switching transistor Q₆ and the second switching transistor Q₇, asin the TTL inverter circuit of FIG. 4. However, the emitter electrode ofthe second switching transistor Q₇ is connected to the emitter electrodeof the transistor Q₄, which is connected to the base electrode of thetransistor Q₅, and the base electrode of the second switching transistorQ₇ is connected to the output terminal OUT. The other parts of thecircuit are the same as that of the circuit of FIG. 4.

In the TTL inverter circuit of FIG. 6, the second switching transistorQ₇ is turned on temporarily by a part of the transient current flowingfrom the point A through the base-emitter junction of the transistor Q₄when the input potential V_(IN) changes from high to low. The otheroperation of the TTL inverter circuit of FIG. 6 is the same as that ofthe TTL inverter circuit of FIG. 4. Therefore, the turn off time of theoutput inverter transistor Q₃ is reduced, and the TTL inverter circuitof FIG. 6 has a sharp transfer characteristic as illustrated in FIG. 5.

FIG. 7 illustrates a TTL inverter circuit as a third embodiment of thepresent invention. The TTL inverter circuit of FIG. 7 comprises a drivertransistor Q₇₁, whose base electrode is connected to the input terminalIN and whose collector electrode is connected to the positive voltagesource V_(cc) through a resistor R₇₁. The TTL inverter circuit of FIG. 7also comprises an output inverter transistor Q₇₂, whose base electrodeis connected to the emitter electrode of the driver transistor Q₇₁,whose emitter electrode is grounded and whose collector electrode isconnected to the output terminal OUT and to the positive voltage sourceV_(cc) through a resistor R₇₂. The TTL inverter circuit of FIG. 7comprises, according to the present invention, a switching transistorQ₇₃ whose main current path is connected between the base electrode andthe emitter electrode of the output inverter transistor Q₇₂ and whosebase electrode is connected, through a capacitor C₇₁, to a terminal Pconnected to a predetermined node in the circuit of FIG. 7. Theswitching transistor Q₇₃ is turned on due to the temporary supply of thebase current through the capacitor C₇₁ when the output invertertransistor Q₇₂ changes from the turned on condition to the turned offcondition. Therefore, the base charge stored in the base region of theoutput inverter transistor Q₇₂ is quickly discharged through the maincurrent path of the switching transistor Q₇₃, as illustrated by an arrowd in FIG. 7, so that the turn off time of the output inverter transistorQ₇₂ is reduced. Therefore, the terminal P is connected to one of thenodes of the circuit of FIG. 7, the potential of which changes from lowto high when the output inverter transistor Q₇₂ changes from the turnedon condition to the turned off condition. For example, the terminal P isconnected to the collector electrode of the driver transistor Q₇₁ or thecollector electrode of the output inverter transistor Q₇₂. A diode D₇₁clamps the potential of the base electrode of the switching transistorQ₇₃ to the ground potential, when the potential of the terminal Pchanges from high level to low level, and ensures quick turn on of theswitching transistor Q₇₃ when the potential of the terminal P changesfrom low level to high level. If the diode D₇₁ is not used, thepotential of the base electrode of the swtiching transistor Q₇₃ falls toa very low level when the potential of the terminal P has changed fromhigh to low, and thus, there is a possibility of missing or delaying theturn on of the switching transistor Q₇₃.

FIG. 8 illustrates a two input DTL NAND gate as a fourth embodiment ofthe present invention. The NAND gate of FIG. 8 is the same as the NANDgate of FIG. 3, except that the diodes D₃₃ and D₃₄ and the resistor R₃₅included in the NAND gate of FIG. 3 are replaced by a capacitor C₈₁ anda Schottky barrier diode D₈₁. In FIG. 8, a terminal of the capacitorC₈₁, which corresponds to the terminal P of the circuit of FIG. 7, isconnected to a node X, i.e., the collector electrode of the drivertransistor Q₃₂. When the output inverter transistor Q₃₃ changes from theturned on condition to the turned off condition, the potential of thenode X changes from low to high and the switching transistor Q₃₆ isturned on for a short time because the base current is temporarilysupplied through the capacitor C₈₁. Therefore, the base charge stored inthe base region of the output inverter transistor Q₃₃ is quicklydischarged and, as a result, the turn off time of the output invertertransistor Q₃₃ is reduced.

With regard to the transfer characteristic, since the NAND gate of FIG.8 does not have a resistor corresponding to the resistor R₅ contained inthe conventional fundamental logic circuit of FIG. 1, the drivertransistor Q₃₂ and the output inverter transistor Q₃₃ turn on or turnoff at substantially the same time. Therefore, the NAND gate of FIG. 8has as sharp a transfer characteristic as that of the logic circuit ofFIG. 4.

The threshold voltage V_(TH) of each of the input potentials V_(IN1) andV_(IN2) of the NAND gate of FIG. 8 is as given by the followingequation.

    V.sub.TH =V.sub.BE32 +V.sub.BE33 -V.sub.F ≈1.2 V   (2)

where V_(BE32) and V_(BE33) are base-emitter voltages of the drivertransistor Q₃₂ and the output inverter transistor Q₃₃, respectively, andV_(F) is a forward biased voltage of the diode D₃₁ or D₃₂. Therefore,the threshold voltage V_(TH) becomes about 1.2 V, and is higher thanthat of the conventional logic circuit of FIG. 3, so that a high noiseimmunity is obtained.

The NAND gate of FIG. 8 also has the following two advantages. One ofthe advantages is low power consumption in a steady state. Thisadvantage is obtained because the base current of the switchingtransistor Q₃₆ flows only temporarily through the capacitor C₈₁ when theoutput inverter transistor Q₃₃ changes from the turned on condition tothe turned off condition. The other of the advantages is that the NANDgate of FIG. 8 does not occupy a large area in a integrated circuit.This is because the NAND gate of FIG. 8 does not use a large number ofparts and the capacitor C₈₁, contained in the NAND gate of FIG. 8, canbe formed by using a multi layer pattern in an integrated circuit.

FIG. 9 illustrates another two input DTL NAND gate as a fifth embodimentof the present invention. The NAND gate of FIG. 9 is the same as theNAND gate of FIG. 8, except that the terminal of a capacitor C₉₁, whichcorresponds to the capacitor C₈₁ in FIG. 8, is connected to a node Y,i.e., the output terminal OUT of the NAND gate of FIG. 9. The potentialof the node Y changes from low to high when the output invertertransistor Q₃₃ changes from the turned on condition to the turned offcondition. Therefore, operation of the NAND gate of FIG. 9 is the sameas that of the NAND gate of FIG. 8, and the NAND gate of FIG. 9 has thesame advantages as that of the NAND gate of FIG. 8.

We claim:
 1. A fundamental logic circuit for performing a fundamentallogic operation comprising:input means for receiving an input signal: adriver transistor having a base electrode connected to said input meansand having emitter and collector electrodes producing output signals; anoutput emitter follower transistor which is driven by the output signalfrom the collector electrode of said driver transistor; an outputinverter transistor having a base electrode which is driven by theoutput signal from the emitter electrode of said driver transistor andwhich comprises a totem-pole output stage together with said outputemitter follower transistor; a first switching transistor which isconnected between the base electrode of said output inverter transistorand ground, and which removes any base charge from the base of saidoutput inverter transistor; and a second switching transistor whosecollector is connected to the base electrode of said first switchingtransistor and whose emitter electrode and base electrode are connectedbetween two nodes of said fundamental logic circuit, the potentialdifference between said two nodes increasing only during a transientperiod in which said output inverter transistor changes from the turnedon condition to the turned off condition, and said first and secondswitching transistors being turned on temporarily in said transientperiod.
 2. A fundamental logic circuit as set forth in claim 1, whereinsaid nodes of said fundamental logic circuit are the collector electrodeof said driver transistor and the emitter electrode of said outputemitter follower transistor, the base electrode of said second switchingtransistor being connected to the emitter electrode of said outputemitter follower transistor.
 3. A fundamental logic circuit as set forthin claim 1, wherein said output emitter follower transistor is aDarlington transistor consisting of first and second transistors, theemitter electrode of said first transistor being connected to the baseelectrode of said second transistor, collector electrodes of said firstand second transistors being connected commonly to each other.
 4. Afundamental logic circuit as set forth in claim 3, wherein said nodes ofsaid fundamental logic circuit are the collector electrode of saiddriver transistor and the emitter electrode of said first transistorcomprising said Darlington transistor, the base electrode of said secondswitching transistor being connected to the emitter electrode of saidfirst transistor comprising said Darlington transistor.
 5. A fundamentallogic circuit as set forth in claim 3, wherein said nodes of saidfundamental logic circuit are the emitter electrode of said firsttransistor comprising said Darlington transistor and the output terminalof said fundamental logic circuit, the base electrode of said secondswitching transistor being connected to an output terminal of saidfundamental logic circuit.
 6. A fundamental logic circuit as set forthin claim 1, 2, 3, 4 or 5 wherein said driver transistor, said outputemitter follower transistor, said output inverter transistor and saidfirst switching transistor are NPN type transistors, and said secondswitching transistor is a PNP type transistor.